1. Field of the Invention
The present invention relates to a method of forming an isolation structure, and more particularly, to a method of forming an isolation structure having a stress.
2. Description of the Prior Art
In recent years, as various kinds of consumer electronic products have constantly developed towards miniaturization, the size of semiconductor components has reduced accordingly in order to meet requirements of high integration, high performance, low power consumption, and demands for more polyvalent products.
In the present semiconductor process, a localized oxidation isolation (LOCOS) or a shallow trench isolation (STI) are normally used to isolate the MOS transistors. However, with the reduction in both design size and fabricating line width of the semiconductor wafer, the drawbacks of pits, crystal defects and longer bird's beak in the LOCOS process will affect even more the characteristics of the semiconductor wafer. The field oxide produced in the LOCOS process also occupies a larger volume, which affects the integration of the semiconductor wafer. Thus, in the submicron semiconductor process, the STI process is widely used as an isolation technique because of its smaller size and improved integration potential.
The typical fabrication method of a STI is to first form shallow trenches between each MOS device in the surface of the semiconductor wafer, and a dielectric matter is filled into the shallow trenches to obtain an electrical isolation effect. Currently, as the sizes of the semiconductor components shrink and get close to their physical limitations, the shallow trench isolation structures with different sizes and the active regions with different sizes dramatically reversely affect the electrical performances of the components and their processing qualities.
As a result, it is still needed to have an STI which has a better quality and be able to improve the electrical performance of the device encompassed by the STI.